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IMP offers three Multimode SCSI
Terminators designed to support the Ultra2 Low Voltage Differential
(LVD) data transmission mode developed by the T-10 standards
group. Multimode devices provide backward compatibility to SCSI-1,
2, 3 and Ultra peripherals. |
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Click here for Single Ended SCSI Terminators
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The IMP5241/5242 differ only in their LOW/HIGH
disconnect polarity. The IMP5241CDB is pin compatible to the
Dallas Semiconductor DS2118ME and the Unitrode UCC5630MWP.
Package options include the 24-pin TSSOP (CPW) and 36-pin SSOP
(CDB). |
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Part
No. |
Package |
Description |
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IMP2119 |
28 TSSOP |
9-Line ULTRA3
LVD/SE SCSI Terminator |
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IMP5241 |
24 TSSOP
36 SSOP |
9-Line Multimode
LVD/SE SCSI Terminator |
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IMP5242 |
24 TSSOP
36 SSOP |
9-Line Multimode
LVD/SE SCSI Terminator |
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IMP5243 |
28 TSSOP |
9-Line Multimode
LVD/SE SCSI Terminator |
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IMP5245 |
24 TSSOP |
LVD SCSI Terminator |
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IMP5246 |
24 TSSOP |
LVD SCSI Terminator |
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Application
Note AN-3: Multimode SCSI Terminators and LVD Signaling |
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All IMP multimode devices feature
auto-selectable LVD or SE (single-ended) termination, high-speed
response without external capacitors and a high bandwidth driver
that reduces channel-to-channel noise and crosstalk. |
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External Capacitors Eliminated |
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External components are minimized.
In the LVD mode, a fast buffer instead of regulators that require
external capacitors supplies the common mode voltage. In SE
mode, the nonlinear adaptive terminator eliminates external
capacitors and more closely matches the loaded SCSI bus impedance.
No external capacitors are required for references or regulators
on the IMP multimode devices. Only a termpower bypass capacitor
is required.
In addition, other IC terminators require an external RC delay
network to accommodate the100mS delay it takes between changes
on the DIFFSENSE line and changes on their outputs. The IMP
multimode parts include an internal digital counter that eliminates
the external RC network. |
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Master/Slave Operation |
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Driving the Master/Slave pin LOW
disables the on-board DIFFSENS reference, allowing the use of
an external master reference. If the Master/Slave pin is allowed
to float or is driven HIGH, the internal DIFFSENSE reference
is active. |
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Automatic Mode Selection |
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Proper mode selection is automatic.
If DIFFSENSE is below 0.5V single-ended operation is selected
and if between 0.7V and 1.9V LVD operation is selected. Outputs
are placed in a high-impedance state when DIFFSENSE is above
2.4V.
A sleep or disable mode reduces supply current to 10 microamperes
maximum and puts the DIFFSENSE and outputs in a high impedance
state. |
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